The IC package substrate is an important component material of the semiconductor package, which is used to carry the chip and provide electrical connection, protection, support and heat dissipation for the chip. In order to achieve the system-level integration requirements of 3D-SiP and meet the needs of high-end applications such as 5G and high-performance computers in the future, the industry has proposed requirements for advanced substrates to increase wiring density, reduce line width and line spacing, reduce size and weight, and improve thermal performance. At present, the research directions of advanced packaging substrates mainly include process improvement, fine circuit, flip chip ball grid array packaging substrate (FCBGA), coreless packaging substrate, embedded substrate of active and passive devices, etc.

1.FCBGA(Flip Chip Ball Grid Array)

FCBGA is currently the most important packaging format for graphics acceleration chips. This packaging technology began in the 1960 s, when IBM developed the so-called C4(Controlled Collapse Chip Connection) technology for the assembly of large computers, and then further developed into the surface tension of molten bumps to support the weight of the chip and control the height of the bumps, and became the development direction of flip chip technology.

The advantages of FCBGA are as follows: The first point is to solve the problem of electromagnetic compatibility (EMC) and electromagnetic interference (EMI). The chip using Wire Bond packaging technology, the signal transmission is carried out through a certain length of metal wire, this method will produce impedance effect at high frequency. However, FCBGA uses small balls instead of the original pins to connect to the processor. This package not only provides excellent electrical performance, but also reduces the loss and inductance between component interconnects, reduces electromagnetic interference problems, and withstands higher frequency. The second point is to increase the I/O density. Generally speaking, the I/O leads using WireBond technology are arranged around the chip, but after FCBGA packaging is adopted, the I/O leads can be arranged on the surface of the chip in an array to provide a higher density I/O layout and produce the best use efficiency. Because of this advantage, the area of flip chip technology is reduced by 30% to 60% compared with the traditional packaging form. The third point is based on FCBGA's unique flip-chip packaging form, the back of the chip can be exposed to air, can directly dissipate heat. At the same time, the substrate can also improve the heat dissipation efficiency through the metal layer, or install a metal heat sink on the back of the chip to further strengthen the heat dissipation ability of the chip and greatly improve the stability of the chip during high-speed operation.

2. Coreless package substrate

The IC package substrate can be classified into a cored substrate and a coreless substrate according to whether there is a core substrate or not. It uses polyimide (Polyimide,PI) with double-sided copper foil as the base material and PI film as the insulating layer to achieve high-density wiring through the additive method. The thickness of the coreless package substrate is only 1/3 of the thickness of the traditional substrate, and the thickness is reduced, which not only makes the coreless substrate more suitable for the trend of light, thin, short and small consumer electronic products, but also makes it have higher signal transmission speed, better signal integrity, lower impedance, freer wiring design, and the ability to achieve finer graphics and spacing. However, due to the lack of mechanical support of the rigid core board, the coreless package substrate has insufficient strength and is easy to warp. How to reduce the warpage in the manufacturing and assembly process has become an important topic in the research and production of coreless package substrates. The common methods to reduce the warpage of coreless package substrate include: adding glass fiber to the prepreg to increase the stiffness, replacing the surface dielectric material of the substrate with a more rigid prepreg, using low thermal expansion coefficient dielectric material to reduce the warpage caused by the mismatch of thermal expansion coefficient between Cu circuit and dielectric material, and developing a suitable fixture for the process to reduce the warpage, balance the copper rate of each layer of the substrate to reduce the mismatch of the thermal expansion coefficient of the upper and lower layers. The following figure shows a method for manufacturing a coreless package substrate.

3. Embedded substrate

According to the types of embedded components, it can be roughly divided into passive component embedding, active device embedding, passive and active hybrid embedding technology and Intel's embedded multi-core interconnection bridge (Embedded Multi-die Interconnect Bridge,EMIB) technology.

3.1 Passive Components Embedded in Substrate Technology

Compared with the traditional technology of soldering all the components to the surface of the PCB board, the technology of embedding the components into the substrate has four advantages. The first point is that it can increase the flexibility and freedom of PCB design and wiring, and can reduce the wiring and shorten the length of the wiring, thus greatly improving the degree of PCB high density. The second point is to improve the high reliability of PCB assembly. Through this process, the welding points on the PCB board surface are significantly reduced, thereby improving the reliability of the assembly board and greatly reducing the probability of failure rate caused by the welding points. The third point is to improve the electrical performance of the PCB assembly, because the passive components are embedded in the high-density PCB, eliminating the connection pads, wires and leads required for discrete passive components. A fourth point is a very significant cost saving of the product or PCB assembly.

3.2 Active Device Embedded Substrate Technology

According to the process sequence of chip embedding, the active device embedding substrate technology can be divided into chip-first embedding technology and chip-last embedding technology. The chip-first embedding technology first embeds the chip in an organic insulating medium, and then makes a circuit pattern to realize signal transmission and power supply. The chip post-type embedding technology first makes a build-up substrate, grooves on the manufactured substrate and makes a circuit pattern, places the chip in the groove, and then uses resin to fill the gap between the chip and the groove body after electrical connection.

Compared with chip-first technology, chip-last technology embedded chip is located in the top layer of the substrate, can be reworked and better heat dissipation, embedded chip after no other substrate layer process steps, processing yield is higher. However, chip-first technology also has its advantages, chip-back technology embedded chip can only be embedded in a layer of chip, and embedded chip substrate surface can no longer mount devices, so the chip-first technology on the substrate space vertical utilization rate is better than the chip-back technology.

3.3EMIB Technology

EMIB is an ultra-thin silicon chip with multi-layer conductive metal (Back End Of Line,BEOL) interconnection embedded in the uppermost layer of the organic packaging substrate, and connected to the flip chip through solder balls to achieve local high-density interconnection between two or more chips. This buried structure can be placed anywhere on the organic substrate to achieve ultra-high density local interconnects, integrating large chips in a range much larger than typical mask sizes, and is very flexible to use. The following figure shows the structure of EMIB technology.